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Junior RTL Design Engineer
Not specifiedFull-timeHardware EngineeringEnterprise SoftwareData Infrastructure
Join a hardware engineering team developing custom ASIC and SoC intellectual property for cloud and consumer products. The role covers microarchitecture, RTL development, verification support, quality checks, and silicon bring-up.
Responsibilities
- Define IP-level microarchitecture specifications, including interfaces, block diagrams, transaction flows, and pipelines.
- Develop and debug RTL using Verilog and SystemVerilog.
- Run functional and performance simulations and RTL quality checks, including Lint, CDC, formal verification, and UPF checks.
- Support synthesis, timing and power closure, and ASIC silicon bring-up.
- Contribute to block- and SoC-level verification plans and coverage analysis.
- Collaborate with architecture, software, verification, power, timing, synthesis, and design-for-test teams.
Requirements
- Bachelor’s degree in electrical engineering, computer engineering, computer science, a related field, or equivalent practical experience.
- At least 4 years of experience with digital logic design, RTL concepts, and Verilog or SystemVerilog.
- Experience with logic design and debug in collaboration with design verification teams.
- Experience developing microarchitecture and technical specifications.
Nice to have
- Experience optimizing RTL for synthesis, performance, power, and area.
- Experience with design sign-off and quality tools such as Lint, CDC, and VCLP.
- Python or Perl scripting experience.
- Knowledge of SoC architecture, assertion-based formal verification, or high-performance and low-power design.
- Knowledge of PCIe, UCIe, DDR, AXI, or ARM processor architectures.