Full-Chip Verification Engineer
Responsible for full-chip verification of next-generation networking silicon. Own verification plans, debug system-level issues, collaborate across teams, and leverage AI tools. Requires B.Sc. in EE/CE and 3-5 years verification experience.
Responsibilities
- Define and drive full-chip verification plans for next-generation NICs.
- Perform system-level debug and analysis of cross-block issues.
- Collaborate with architecture, micro-architecture, and firmware teams.
- Leverage AI coding tools and frameworks to accelerate development.
Requirements
- B.Sc. in Electrical Engineering or Computer Engineering with high scores or equivalent experience.
- 3-5 years of experience in verification or hardware simulation.
- Strong debugging, problem-solving, and analytical skills.
- Proactive innovation mindset with adoption of new methodologies and tools.
- Team player with good communication and interpersonal skills.
Nice to have
- Prior verification experience of SoC.
- Knowledge in network flows and protocols.