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Senior Physical Design Engineer
לא צויןמשרה מלאהHardware Engineering
A semiconductor engineering team is seeking a senior physical design engineer to deliver complex, high-performance SoCs through tape-out on advanced FinFET process nodes. The role combines hands-on implementation, signoff, clocking, automation, and collaboration with ASIC foundries or design service
תחומי אחריות
- Execute physical design and backend implementation for advanced SoCs.
- Design, synthesize, and debug clock networks, including H-trees and clock meshes.
- Resolve skew, jitter, dynamic voltage drop, power distribution, and high-frequency routing challenges.
- Drive timing closure and advanced signoff activities for multi-voltage and power-gated designs.
- Manage physical design tool flows and automation infrastructure.
- Coordinate with ASIC vendors and design service providers on rules, signoff, and handoff requirements.
- Support complex SoC tape-outs while balancing design optimization and schedule demands.
דרישות
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
- At least 5 years of hands-on physical design and backend implementation experience.
- Successful tape-out of complex, multi-million-gate SoCs on advanced FinFET nodes such as 7nm, 5nm, or 3nm.
- Deep experience designing, synthesizing, and debugging H-tree and clock-mesh architectures, including skew, jitter, dynamic voltage drop, and power distribution issues.
- Expertise with physical design and synthesis flows using tools such as Synopsys Fusion Compiler, Innovus, Design Compiler NXT, PrimeTime, and Calibre.
- Experience collaborating with major ASIC foundries or turnkey design service providers on physical design rules and handoff requirements.
- Strong knowledge of timing closure, multi-voltage and power-gated designs using UPF or CPF, and high-frequency routing.
- Strong Tcl, Python, or Perl scripting skills for developing and maintaining physical design infrastructure and tool flows.
- Ability to work pragmatically in a fast-paced, high-ambiguity startup environment.