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Lead globally distributed front-end SoC engineering teams responsible for RTL design and design verification in a complex MCU development environment.

Lead a team of physical design engineers in the development of complex SoC architectures. Oversee all PD activities including synthesis, place and route, power verification, and static timing analysis. Work closely with RTL and cross-functional teams.

Lead development and integration of ultra-low power technology for next-generation SoC designs. Responsibilities include circuit and analog chip design, algorithm development, and validation. Requires 10+ years experience and proficiency with RTL, Verilog, STA, and Cadence Virtuoso.