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Senior Analog Design Engineer
Sin especificarTiempo completoHardware EngineeringSemiconductor ManufacturingComputers and Electronics ManufacturingSoftware Development
Lead development and integration of ultra-low power technology for next-generation SoC designs. Responsibilities include circuit and analog chip design, algorithm development, and validation. Requires 10+ years experience and proficiency with RTL, Verilog, STA, and Cadence Virtuoso.
Responsabilidades
- Lead next generation algorithm development for ultra-low-power technology
- Lead integration of technology into new SoC designs
- Perform circuit and analog chip design tasks
- Validate new developments
Requisitos
- Minimum of 10 years of experience
- Knowledge of circuit design
- Knowledge of RTL coding (Verilog)
- Knowledge of Static Timing Analysis (STA) flow
- Good system view and HW-SW tasks separation
- Experience with Cadence Virtuoso design and simulation tools
- Excellent communication skills with multinational teams
- Independent and team player
- BSc in Electrical Engineering
Se valora
- Knowledge of analog design
- Knowledge of ultra-low power design techniques
- Knowledge of Skill and Python programming languages
- MSc in Electrical Engineering