Empleos de Hardware Engineering en Israel

Join a semiconductor engineering team developing processor platforms for large-scale cloud infrastructure. Own SoC development from microarchitecture through tape-out and collaborate across verification, physical design, product definition, and software teams.

An electronics engineering employer in Rehovot is seeking a full-time Junior DFT Engineer to develop diagnostic tests and troubleshoot electronic boards and assemblies.

Join a quantum hardware R&D team in Tel Aviv designing and simulating superconducting qubits and circuit elements for quantum processors.

A health technology company is seeking a Senior FPGA Design Engineer in Haifa to develop, optimize, integrate, and validate FPGA solutions for CT and imaging systems. The role is office-based with at least three days per week onsite and includes a monthly salary range of ILS 21,515–35,858 plus bonus

Lead end-to-end hardware architecture and implementation for high-throughput wireless communication systems using AMD Xilinx RFSoC and MPSoC platforms.

Join a hardware engineering team developing custom ASIC and SoC intellectual property for cloud and consumer products. The role covers microarchitecture, RTL development, verification support, quality checks, and silicon bring-up.

Join a hardware engineering team developing custom ASIC and SoC intellectual property for cloud and consumer products. The role covers microarchitecture, RTL development, verification support, quality checks, and silicon bring-up.

Lead power engineering execution for advanced switch ASICs from architecture through tape-out and into post-silicon production support. The role coordinates multidisciplinary engineering teams and manages ASIC power planning, modeling, optimization, and analysis.

Join an advanced hardware engineering team developing functional models and simulators for next-generation networking switches. The role connects hardware architecture and software, enabling design teams to explore, validate, and shape system behavior.

Develop physical design, static timing analysis, logic equivalence, power integrity, and backend verification flows for networking chips and SoCs.