Senior FPGA and System Architecture Engineer
Lead end-to-end hardware architecture and implementation for high-throughput wireless communication systems using AMD Xilinx RFSoC and MPSoC platforms.
Responsabilidades
- Own full-chip system architecture on AMD Xilinx RFSoC platforms.
- Translate floating-point MATLAB and C++ models into fixed-point, resource-optimized, bit-exact SystemVerilog RTL.
- Design and integrate high-throughput physical-layer pipelines.
- Architect PCIe connectivity between RFSoC devices, host CPUs, and GPU accelerators.
- Implement deterministic data streaming and low-latency DMA transfers.
- Lead bit-accurate simulation, hardware emulation, and laboratory bring-up.
- Use Vivado, logic analyzers, and RF test equipment to validate timing, throughput, and system performance.
Requisitos
- Hands-on experience architecting and delivering production designs on AMD Xilinx Zynq UltraScale+ RFSoC or MPSoC platforms.
- Expert proficiency in synthesizable SystemVerilog or Verilog.
- Experience with high-speed pipelining and timing closure in congested designs.
- Experience implementing high-bandwidth PCIe Gen3 or Gen4 subsystems and DMA engines such as XDMA or QDMA.
- Knowledge of PCIe link training, enumeration, boot sequencing, and backpressure management.
Se valora
- Experience integrating AMD Xilinx RF-Data Converters and digital down- and up-conversion chains.
- Experience implementing fixed-point wireless communication algorithms, including filter banks, DDC/DUC, FFT/IFFT, channel estimation, and correlation.
- Familiarity with Linux kernel or user-space drivers, DPDK, VFIO/UIO, or embedded ARM software for hardware-software coordination.