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Staff RTL Design Engineer
Sin especificarTiempo completoHardware EngineeringCloud Computing
Design high-performance ASICs for cloud infrastructure. Contribute to all phases from specification to production, including RTL development, synthesis, timing/power closure, and verification. Collaborate with architecture, software, and verification teams.
Responsabilidades
- Define block-level design documents (interface protocol, block diagram, transaction flow, pipeline).
- Perform RTL development (coding and debug in Verilog/SystemVerilog/VHDL), and run Lint/CDC/FV/UPF checks.
- Support synthesis, timing/power closure, and FPGA/silicon bring-up.
- Participate in test plan and coverage analysis for block and SoC-level verification.
- Communicate and collaborate with multi-disciplined and multi-site teams.
Requisitos
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- Experience with ASIC design verification, synthesis, timing/power analysis, and DFT.
- Experience with Verilog/SystemVerilog, VHDL, or Chisel.
- Experience with SoC development cycles.
Se valora
- Proficiency in scripting (Python or Perl).
- Knowledge of high-performance and low-power design techniques.
- Knowledge of assertion-based formal verification.
- Knowledge of FPGA and emulation platforms.
- Knowledge of SoC architecture.
- Knowledge in arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.