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Senior SoC and IP Design Engineer
PresencialTiempo completoHardware Engineering
Senior engineer with 8+ years of experience in digital logic design, RTL coding, and SoC/IP architecture. Responsible for block-level design, synthesis, timing closure, and verification, collaborating across multi-site teams.
Responsabilidades
- Define block-level design documents including interface protocol, block diagram, and transaction flow.
- Perform RTL coding and debug in Verilog/SystemVerilog, and run Lint/CDC/FV/UPF checks.
- Participate in synthesis, timing, and power closure activities.
- Contribute to test plan and coverage analysis for block and SoC-level verification.
- Collaborate with multi-disciplined and multi-site teams.
Requisitos
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance, and power, as well as low-power design techniques.
- Experience with design sign-off and quality tools (e.g., Lint, CDC).
- Experience with SoC or IP architecture.
Se valora
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SoC architecture.
- Knowledge of DDR/LPDDR or HBM.
- Excellent problem-solving and debugging skills.