Senior RTL Design Engineer
Join a semiconductor engineering team developing high-performance CPU cores. The role focuses on microarchitecture, RTL implementation, validation, debug, and tape-in readiness in a hybrid Haifa-based environment.
Responsabilidades
- Define microarchitecture for allocation and resource-management mechanisms in high-performance CPU cores
- Develop RTL using SystemVerilog
- Own features from architecture exploration through RTL development, validation support, debug, and tape-in readiness
- Lead significant design efforts and evaluate microarchitectural trade-offs
- Collaborate with architecture, verification, physical design, power-performance, and post-silicon teams
Requisitos
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field
- At least 5 years of RTL logic design and development experience using SystemVerilog
- Strong knowledge of computer architecture, microarchitecture, and digital design principles
- Experience defining and implementing complex microarchitectural features
- Strong debugging and problem-solving skills
- Ability to drive features from definition through implementation and validation
- Effective communication and collaboration skills
Se valora
- Design partitioning and microarchitectural trade-off analysis
- Functional validation and coverage planning with verification teams
- High-performance CPU or cache and memory subsystem design
- Timing closure, power optimization, and performance analysis
- Power-aware RTL coding and power debugging
- Post-silicon debug and bring-up
- Design methodologies, scripting, and automation
- Experience with geographically distributed, cross-functional engineering teams