G
Senior Networking ASIC Design Engineer
PresencialTiempo completoHardware EngineeringCloud ComputingSemiconductors
Design and develop networking ASIC subsystems from specifications through production for high-performance cloud and consumer infrastructure. The role covers micro-architecture, RTL development, verification, synthesis, timing closure, and silicon bring-up, with work across distributed hardware and15
Responsabilidades
- Define block-level design documents, including interface protocols, block diagrams, transaction flows, and pipelines
- Develop and debug RTL using Verilog, SystemVerilog, or VHDL
- Perform functional and performance simulation debugging and run Lint, CDC, formal verification, and UPF checks
- Participate in synthesis, timing and power analysis, and FPGA or silicon bring-up
- Contribute to block- and SoC-level test planning and coverage analysis
- Collaborate with multidisciplinary and distributed teams
Requisitos
- Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience
- At least 8 years of experience architecting networking ASICs from specification through production, or equivalent experience
- Experience developing RTL for ASIC subsystems
- Experience with micro-architecture, design, verification, logic synthesis, and timing closure
Se valora
- Experience with RDMA, packet processing, or low-latency, high-throughput networking systems
- Experience architecting networking switches, endpoints, or hardware offloads
- Experience optimizing hardware/software interfaces with software teams
- Experience with C++, Python, or Go
- Knowledge of TCP/IP, Ethernet, PCIe, and DRAM
- Familiarity with NoC principles and AXI, ACE, or CHI protocols