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Senior FPGA Verification Engineer
Sin especificarTiempo completoHardware EngineeringAerospace and Defense
Work in a multidisciplinary engineering team developing advanced missile and space systems. Build and run FPGA verification environments, support legacy environments, and contribute to design validation, laboratory testing, integration, and technical documentation.
Responsabilidades
- Build and run random-based verification environments for programmable components and modules.
- Apply SystemVerilog UVM methodologies from specification through functional coverage.
- Maintain and support legacy Verilog, VHDL, and SystemVerilog verification environments.
- Write TCL and Python scripts.
- Validate designs in the laboratory and prepare test documentation.
- Collaborate with internal and external stakeholders on technical specifications and system integration.
Requisitos
- Bachelor’s degree in electrical and electronics engineering.
- At least 3 years of FPGA verification experience.
- Demonstrated knowledge of signal processing and control.
- Experience developing reusable verification environments with UVM.
- Experience integrating verification environments.
- Experience implementing and reporting functional coverage.
- Experience with UVM scoreboards and/or UVM Register Model.
- Working knowledge of SystemVerilog, Verilog, VHDL, TCL, and Python.
Se valora
- Experience with assertion-based verification.
- Knowledge of VIPs and verification-environment integration.
- Familiarity with AXI, SPI, I2C, Ethernet, or PCIe communication protocols.
- Experience with VHDL or Verilog design-development processes.