M
Senior Design Engineer
Sin especificarTiempo completoHardware EngineeringSemiconductor Manufacturing
Responsible for leading the design of digital blocks from architecture to implementation, driving area and timing optimization, lint, CDC/RDC analysis, and collaborating on block-level verification. Requires a B.Sc/M.Sc in Electrical Engineering and 5+ years of digital design experience with proficiency in Verilog/SystemVerilog.
Responsabilidades
- Take ownership of key digital blocks, leading design from architecture definition through implementation
- Drive all aspects of block design including area and timing optimization, lint, and CDC/RDC analysis
- Work closely with verification engineers to support and contribute to block-level verification
Requisitos
- Bachelor's or Master's degree in Electrical Engineering
- 5+ years of experience in digital design
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with linting, CDC/RDC, synthesis, timing closure, power optimization, and backend flows
- Strong problem-solving and analytical skills
- Ability to understand complex systems
- Excellent collaboration and communication skills
Se valora
- Experience with SystemVerilog and UVM for verification