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Senior ASIC Design Engineer
PresencialTiempo completoHardware EngineeringNetworking Equipment
Join a front-end silicon design team developing advanced, programmable networking devices. Own RTL implementation, integration, timing analysis, verification collaboration, and lab validation.
Responsabilidades
- Write and review micro-architecture specifications
- Implement Verilog/SystemVerilog RTL to meet timing, performance, and power targets
- Contribute to full-chip integration, timing methodology, and analysis
- Collaborate with verification engineers to resolve bugs and achieve coverage closure
- Work with physical design engineers on timing and place-and-route issues
- Improve design methodologies and engineering best practices
- Perform debugging, root-cause analysis, and post-silicon laboratory validation
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering from a leading university
- At least 8 years of relevant experience
- Professional RTL design experience
- Familiarity with UVM and functional verification methodologies
Se valora
- MATLAB simulation and bit-exact modeling experience
- Experience with mixed-signal systems
- Knowledge and hands-on experience with Clock Domain Crossing (CDC)