G
Senior ASIC CAD Engineer
Sin especificarTiempo completoHardware EngineeringCloud ComputingConsumer Internet
Develop and maintain front-end CAD flows and methodologies for SoC designs, helping improve RTL quality, verification, and engineering efficiency.
Responsabilidades
- Architect, deploy, and maintain scalable front-end CAD flows for SoC design, including build, IP delivery, linting, CDC, RDC, and logic synthesis.
- Develop methods to detect RTL quality issues early and reduce design iterations.
- Evaluate and deploy third-party EDA tools and work with vendors to resolve technical issues and improve tools.
- Collaborate with RTL design, verification, and physical design teams to remove bottlenecks and establish best practices.
- Integrate AI/ML-driven flows and agentic workflows to automate verification, improve coverage closure, and optimize bug detection.
Requisitos
- Bachelor’s degree in electrical engineering, computer science, computer engineering, or a related field, or equivalent practical experience.
- At least 8 years of experience in front-end ASIC design, CAD, or methodology development.
- Experience scripting and automating with languages such as Python or Tcl.
Se valora
- Familiarity with Git and CAD data management.
- Understanding of RTL coding styles, synthesizability, and design-for-verification practices.
- Experience architecting and improving complex engineering workflows.