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RTL Design Technical Lead – Networking ASICs
PresencialTiempo completoHardware EngineeringEnterprise SoftwareData Infrastructure
Lead the architecture and RTL development of networking ASIC subsystems and SoC blocks, collaborating with cross-functional teams throughout the design cycle from specification to production. The role is based in Israel, with work locations available in Tel Aviv or Haifa and in-person interviews may
Responsabilidades
- Define block-level architecture and design documentation, including interface protocols, block diagrams, transaction flows, and pipelines
- Develop and debug RTL using Verilog, SystemVerilog, or VHDL
- Run functional and performance simulations and perform Lint, CDC, formal verification, and UPF checks
- Participate in synthesis, timing and power analysis, and FPGA or silicon bring-up
- Contribute to test planning and block- and SoC-level verification coverage analysis
- Collaborate with architecture, software, verification, power, timing, synthesis, and distributed engineering teams
Requisitos
- Bachelor’s degree in electrical engineering, computer engineering, computer science, a related field, or equivalent practical experience
- At least 10 years of experience architecting networking ASICs from specification through production
- At least 8 years of technical leadership experience
- Experience with arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
- Experience developing RTL for ASIC subsystems
Se valora
- Experience with RDMA, packet processing, and low-latency, high-throughput system design
- Knowledge of TCP/IP, Ethernet, PCIe, DRAM, NoC, AXI, ACE, and CHI protocols
- Experience architecting networking switches, endpoints, and hardware offloads
- Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry