Q
Junior Physical Design Engineer
Sin especificarTiempo completoHardware EngineeringSemiconductor Manufacturing
Join an ASIC physical design team implementing and verifying complex digital designs from netlist to GDSII across advanced FinFET process technologies. The role supports backend design flows, timing closure, physical verification, automation, and cross-functional handoffs.
Responsabilidades
- Support floorplanning, placement, clock tree synthesis, and routing under senior engineer guidance
- Assist with timing closure, static timing analysis, path debugging, and constraint verification
- Run and analyze IR drop, signal integrity, and electromigration reports
- Execute DRC, LVS, and DFM physical verification flows and triage violations
- Develop and maintain Python and TCL scripts for report parsing, constraint generation, and batch runs
- Contribute to physical design flow development and document automation scripts and runsets
- Explore AI-assisted tools for constraint checking, violation triage, and design-space exploration
- Collaborate with front-end, DFT, and verification teams on design handoffs and ECO implementation
Requisitos
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Science, or a related field
- 0–3 years of digital physical design experience; academic projects and internships are considered
- Basic understanding of floorplanning, placement and routing, clock tree synthesis, and static timing analysis
- Familiarity with at least one EDA tool, such as Synopsys ICC2, Cadence Innovus, Calibre, or PrimeTime
- Ability to read, modify, and write Python or TCL scripts
- Willingness to learn advanced TSMC N5, N4P, and N3 FinFET process technologies
- Analytical and problem-solving skills
Se valora
- Exposure to TSMC advanced-node design rules
- Familiarity with DFT concepts, including scan and ATPG
- Coursework or project experience applying AI/ML to EDA or flow automation