Junior Physical Design Engineer
Join a networking silicon team developing high-speed communication devices. Work across chip physical design, from RTL to GDS, with a focus on power, performance, and area.
Responsabilidades
- Perform block-level physical design to meet specifications and power, performance, and area constraints.
- Work on synthesis, power and clock distribution, place and route, and timing closure.
- Analyze power and noise, and perform physical verification.
- Resolve timing and congestion challenges across varied designs.
- Contribute to flow development.
Requisitos
- Bachelor’s or master’s degree in electrical or computer engineering, or equivalent experience.
- Proven experience with RTL-to-GDS flows and methodologies.
- Knowledge of physical design flows, including place and route, static timing analysis, and physical verification.
- Understanding of physical construction and integration.
Se valora
- Familiarity with physical design EDA tools such as Synopsys or Cadence.
- Experience with LVS/DRC verification methodologies.