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Design Verification Engineer
Sin especificarTiempo completoHardware EngineeringInformation TechnologyCloud ComputingAISemiconductorsInternet
Responsible for verifying digital designs, developing constrained-random test environments, and driving system testing to closure. Collaborate with design teams, manage verification life-cycle, and ensure functional correctness through corner-case testing.
Responsabilidades
- Plan and execute verification of digital design blocks by understanding specifications and defining key verification scenarios.
- Develop and refine random verification environments using SystemVerilog/UVM or Specman.
- Define and implement coverage measures to capture stimulus and corner-case scenarios.
- Collaborate with design engineers to debug tests and ensure functional correctness.
- Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.
Requisitos
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 4 years of experience verifying digital logic at RTL using SystemVerilog or Specman/E for FPGAs or ASICs.
- Experience with CPU implementation, assembly language, or compute SoC.
- Experience verifying digital systems using standard IP components/interconnects.
- Experience creating and using verification components and environments in standard verification methodology.
Se valora
- Master’s degree in Electrical Engineering or Computer Science.
- 2 years of experience verifying digital logic at RTL using SystemVerilog or Specman/E for FPGAs or ASICs.
- Experience with UVM, SystemVerilog, or scripting languages like Python, Perl, Shell, Bash.