Principal Silicon Design Verification Manager
Lead a multidisciplinary silicon engineering team and own verification strategy for complex, security-oriented subsystems from planning through closure and emulation readiness. Combine people leadership with hands-on technical contribution and improve verification workflows, including AI-assisted, U
Обязанности
- Lead, grow, and mentor design verification, silicon design, and physical design engineers
- Own verification strategy from planning and execution through closure and emulation readiness
- Provide hands-on leadership in verification planning, testbench architecture, debugging, coverage analysis, regression quality, and closure
- Define verification plans, quality metrics, regression strategy, coverage goals, and emulation readiness plans
- Develop modern verification workflows and AI-assisted techniques for automation, debugging, coverage, and productivity
- Partner with architecture, design, system engineering, firmware, and physical design teams to identify risks and resolve issues
Требования
- Bachelor's, master's, or doctoral degree in electrical engineering, computer engineering, or a related technical field
- Significant experience in pre-silicon design verification for complex IP, subsystems, or SoCs
- Experience with subsystem integration and third-party IP integration
- Hands-on experience with verification planning, testbench development, regressions, coverage analysis, debugging, and verification closure
- Experience as a people manager or technical leader guiding multiple engineers
Будет плюсом
- SystemVerilog, UVM, assertions, constrained-random, and coverage-driven verification experience
- Python, Linux, Git, and verification automation infrastructure experience
- Experience with AI-assisted verification techniques
- Formal, low-power, performance, or subsystem-level verification experience
- Experience with security-oriented silicon, including cryptography, memory protection, secure boot, or trusted execution
- Experience with Palladium or other emulation platforms
- Familiarity with physical design, synthesis, constraints, timing closure, or handoff flows