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Senior Engineering Manager, DPU Performance and System Validation
В офисеПолная занятостьHardware EngineeringElectronics Manufacturing
Lead a team of 25+ engineers across performance verification, simulation modeling, and system validation for DPU chip development in Israel.
Обязанности
- Lead and manage 25+ engineers across performance, simulation model, and system validation teams
- Collaborate with architecture teams to define and implement performance verification plans
- Coordinate performance emulation and functional validation through tapeout readiness
- Support post-silicon performance debugging and improvement initiatives
- Develop and standardize performance debugging processes across platforms
Требования
- 15+ years of experience in ASIC development and validation
- 5+ years of engineering management experience
- Experience managing performance within chip development
- Technical expertise in DPU performance and system validation
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or an equivalent field
- Strong cross-functional collaboration and team leadership skills