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Physical Design Engineer
Не указаноПолная занятостьHardware EngineeringSemiconductors
Design and implement SOC-level clock distribution for advanced networking chips. Work on chip-level partitioning, CDC, synthesis, and design quality. Collaborate across functional teams to address physical design readiness and debug challenges.
Обязанности
- Design and implement SOC-level clock distribution requirements
- Perform chip-level partitioning, CDC, trial synthesis, and design quality checks
- Address functional debug and physical design readiness issues
Требования
- B.Sc. in Electrical Engineering or Computer Engineering
- 3+ years of experience in chip design
- Hands-on physical design experience with clock distribution in multi-power, timing-constrained products
- Proficiency in at least one scripting language (Perl, Python, Bash, Tcl)
- Strong teamwork and collaboration skills
Будет плюсом
- Passion for quality and attention to detail
- Experience delivering designs back to RTL, physical design, and other teams
Условия и преимущества
- Competitive salaries and comprehensive benefits package