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Junior SoC IP Design Engineer
В офисеПолная занятостьHardware EngineeringInformation Technology
Join a team developing custom silicon solutions for direct-to-consumer products. As a Junior SoC IP Design Engineer, you will define design documents, perform RTL coding in Verilog/SystemVerilog, participate in verification and ASIC bring-up, and collaborate with multi-disciplinary teams.
Обязанности
- Define SoC/block-level design documents including interface protocols, block diagrams, transaction flows, and pipelines.
- Develop RTL code in Verilog/SystemVerilog, debug simulations, and run Lint, CDC, FV, and UPF checks.
- Participate in synthesis, timing/power closure, and ASIC silicon bring-up.
- Contribute to test planning and coverage analysis for block and SoC-level verification.
- Collaborate with multi-disciplinary teams across sites.
Требования
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
- At least 1 year of experience with digital logic design, RTL design concepts, and Verilog/SystemVerilog.
- Experience with design sign-off and quality tools (Lint, CDC, etc.).
Будет плюсом
- Master's or PhD in Computer Science or related technical field.
- Knowledge in PCIe, UCIe, DDR, AXI, or ARM processors.
- Knowledge of high-performance and low-power design techniques.
- Knowledge of assertion-based formal verification.
- Knowledge of SoC architecture.
- Strong problem-solving and debugging skills.