Вакансии: Разработка

A networking design team seeks an STA engineer to perform static timing analysis and support DFT physical design for high-speed communication chips.

Develop AI methods and tools for chip verification, automating test generation, coverage closure and debugging. Apply machine learning and LLMs to improve pre-silicon verification workflows.

Own clocking and reset logic for next-generation networking SoCs, taking synthesizable RTL from micro-architecture through verification, physical design, and tape-out.

Own SOC clocking and reset logic for next-generation networking chips, taking synthesizable RTL from micro-architecture specification through physical implementation and tape-out in collaboration with cross-functional engineering teams.

Join a networking silicon team to optimize power across physical design and contribute to chip development from RTL to GDS.

Define software and system architecture for next-generation DPU management and networking platforms supporting large-scale AI and cloud datacenters. Partner across hardware, software, firmware, validation, product, and customer teams from early design through production readiness.

Join an engineering team designing and verifying signal and power integrity for electronic systems, from concept through release.

Own software and system architecture for DPU management, QoS, performance, telemetry, and observability features. Work across software, firmware, hardware, validation, product, and customer teams from early architecture through production readiness for AI and cloud datacenters.

Join a software architecture team shaping networking devices and data center platforms. Work with system architects and software, firmware, hardware, and product teams to develop component-level and system-level designs.

Join a networking hardware team to define future network adapter chip architectures and build simulation tools that guide design and performance decisions.