A
Verification Engineer
·Israel
Not specifiedPart-timeHardware EngineeringInformation Technology & Services
Seeking a Verification Engineer to build and maintain SystemVerilog/UVM environments, write testbenches and simulations, debug ASIC/SoC designs, and track coverage. Requires 3+ years of verification experience and a B.Sc. in EE/CE.
Responsibilities
- Build and maintain SystemVerilog/UVM environments, write testbenches, simulations, and regressions.
- Analyze specifications, create verification plans, drive debug and bug fixing to closure.
- Track functional/code coverage, document flows, and improve team productivity.
- Context-switch across blocks, support integration, and handle ad-hoc scripting/automation.
Requirements
- 3+ years of verification experience in ASIC/SoC.
- Strong SystemVerilog/UVM skills.
- Experience with Verdi, Questa, or VCS.
- Proven self-learning, flexibility, and ownership of undefined work.
- Clear teamwork and communication skills.
Nice to have
- Familiarity with AMBA/AXI/AHB, PCIe, Ethernet protocols.
- Scripting in Python, Perl, or Tcl.
- Experience with Git and Jira.