Staff ASIC Design Engineer
Lead ASIC subsystem design for data center networking accelerators. Define microarchitecture, RTL, and hardware-software interfaces. Collaborate with software, verification, and physical design teams to deliver performant, reliable networking silicon.
Responsibilities
- Lead ASIC subsystem design and implementation.
- Understand interactions with software and other ASIC subsystems to implement data center networks.
- Define hardware/software interfaces and write microarchitecture and design specifications.
- Define efficient microarchitecture, block partitioning, and interfaces.
- Collaborate with software, verification, and physical design stakeholders to ensure design completeness, correctness, and performance.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
- 10 years of experience architecting networking ASICs from specification to production.
- Experience developing RTL for ASIC subsystems.
- Experience with cross-functional engagement in microarchitecture, design, verification, logic synthesis, and timing closure.
Nice to have
- Experience working with software teams optimizing the hardware/software interface.
- Experience architecting networking switches, endpoints, and hardware offloads.
- Experience with RDMA or packet processing and system design for low latency, high throughput, security, and reliability.
- Experience in TCP, IP, Ethernet, PCIe, DRAM, and NoC protocols (AXI, ACE, CHI).
- Proficiency in C++, Python, or Go.
- Understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.