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STA Physical Design Engineer
·Israel
On-siteFull-timeHardware EngineeringComputer Hardware Manufacturing
Join a team developing high-speed communication devices, focusing on DFT STA execution from RTL constraints to sign-off, timing ECO generation, and flow development.
Responsibilities
- Execute DFT STA from RTL-driven constraints through timing sign-off
- Perform static timing analysis including constraints, environment, and models generation
- Generate timing ECO for block and full chip level
- Develop and improve STA flows
- Collaborate with cross-functional teams on pre- and post-silicon design aspects
Requirements
- B.Sc. in Electrical Engineering or Computer Engineering
- 2-3 years of experience as an STA engineer
- Strong communication and teamwork skills
- Ability to quickly adapt to new technologies and drive new solutions
Nice to have
- Knowledge of physical design flows and methodologies (PNR, STA, physical verification)
- Experience with DFT flows such as ATPG, MBIST, IJTAG
- Prior experience in DFT timing closures
- Knowledge of CDC (Clock Domain Crossing)
- Familiarity with physical design EDA tools (Synopsys, Cadence, etc.)