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Senior Staff Physical Design Engineer
·Israel
Not specifiedFull-timeHardware EngineeringTelecommunications
Architect and own full-chip physical design strategies, including floorplanning, power delivery, clock architecture, and timing closure. Lead methodology standards, automation flows, and agentic AI adoption. Mentor engineers and collaborate across functions.
Responsibilities
- Architect and own full-chip physical design strategy: floorplanning, PDN, clock architecture, PnR, and timing closure.
- Define and drive backend methodology standards for advanced node tapeouts.
- Lead critical timing closure efforts including MCMM, OCV, ECO strategies, and cross-corner sign-off.
- Oversee signal integrity, power integrity, EM/IR, and reliability analysis.
- Architect scalable PD flow infrastructure using Python and TCL.
- Champion adoption of Agentic AI in the design flow.
- Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams.
- Interface with TSMC, EDA vendors, and internal research teams.
- Mentor and guide junior and mid-level PD engineers.
Requirements
- 10+ years of experience in digital Physical Design with FinFET node tapeouts.
- Deep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off.
- Expert proficiency in EDA tools: Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk/Voltus, StarRC/Quantus.
- Advanced Python and TCL scripting for PD automation frameworks.
- Proven experience in end-to-end backend design flow development.
- Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges.
- Strong communication skills.
Nice to have
- Experience with chiplets, 2.5D/3D IC physical design, or advanced packaging.
- Familiarity with AI/ML-driven EDA tool evaluation.
- Prior tech lead or staff engineering leadership role.