Senior Staff Design Verification Engineer
Seeking a Senior Staff Design Verification Engineer to develop and verify cutting-edge networking silicon for AI and cloud data centers. The role involves building testbenches, collaborating across architecture and firmware teams, and driving verification for high-performance compute platforms.
Responsibilities
- Develop and maintain verification environments using SystemVerilog and UVM
- Build reference models and testbenches for complex silicon designs
- Collaborate with architecture, firmware, and post-silicon teams across the development cycle
- Lead verification initiatives and drive resolution of complex technical challenges
- Mentor team members and foster knowledge sharing
Requirements
- B.Sc. or M.Sc. in Computer Science, Electrical Engineering, or a related field
- At least 5 years of professional experience with Verilog and SystemVerilog/UVM
- Proven expertise in testbench and verification environment development
- Working knowledge of the Linux operating system
- Strong analytical and problem-solving skills with a strategic mindset
- Demonstrated ability to lead initiatives and take ownership of complex challenges
- Strong interpersonal skills for effective cross-functional collaboration
Benefits
- Competitive compensation and benefits package
- Collaborative and transparent work environment
- Opportunities for professional growth and development