G
Senior RTL Design Engineer
·Israel
On-siteFull-timeHardware EngineeringCloud ComputingInformation Technology
Lead complex ASIC subsystem development, define microarchitecture and RTL design, and collaborate with cross-functional teams to deliver high-performance System-on-Chip solutions for data center infrastructure.
Responsibilities
- Lead the development of a complex ASIC subsystem.
- Define hardware/software interfaces and write microarchitecture and design specifications.
- Develop efficient microarchitecture, block partitioning, interfaces, and design flows.
- Collaborate with software, verification, and physical design teams to ensure design completeness, correctness, and performance.
- Understand subsystem interactions with software and other ASIC subsystems for data center implementations.
Requirements
- Bachelor's degree in Electrical Engineering or equivalent experience.
- 5+ years of RTL development experience for ASIC subsystems using Verilog.
- Experience with high-speed interfaces (PCIe, InfiniBand) and related principles.
- Experience in microarchitecture, design, verification, logic synthesis, and timing closure.
Nice to have
- Experience with scripting languages such as Python or Perl.
- Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
- Knowledge of high-performance and low-power design techniques.
- Familiarity with FPGA, emulation platforms, and SoC architecture.
- Knowledge of assertion-based formal verification.