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Senior RTL Design Engineer
·Israel
On-siteFull-timeHardware EngineeringCloud ComputingArtificial Intelligence
Responsible for designing and implementing high-speed digital signal processing blocks for custom ASICs, focusing on RTL design, microarchitecture, and front-end implementation flow to achieve timing closure at GHz frequencies on advanced process nodes. Collaborate with verification teams to ensure bit-exact functionality.
Responsibilities
- Design and implement high-speed digital blocks, taking end-to-end ownership of complex modules.
- Resolve implementation challenges related to GHz-frequency timing closure and advanced process nodes.
- Transform architectural specifications and communication theory models into efficient, bit-exact RTL implementations.
- Perform fixed-point analysis and micro-architectural trade-offs to optimize design.
- Execute and optimize the front-end design flow to ensure sign-off quality designs.
- Collaborate with verification teams to develop bit-exact C++/SystemC models and ensure seamless integration.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
- 8 years of experience in digital signal processing (DSP) design or high-speed digital logic design.
- Experience implementing digital blocks for communication systems or PHY (e.g., filters, interpolators, timing recovery).
- Experience with MATLAB, Python, or C++.
Nice to have
- Master's or PhD in Electrical Engineering, Computer Engineering, or related field.
- Experience with full front-end design flow: Synthesis, STA, CDC/LEC.
- Experience with advanced FinFET process nodes (5nm, 3nm) and timing closure at GHz frequencies.
- Experience with high-speed serial links (SerDes) and FEC implementation.
- Understanding of low-power design techniques and dynamic power optimization.