Senior IC Packaging Design Engineer
Design complex IC substrate layouts and high-speed interconnect packages for networking systems, collaborating with signal integrity, power integrity, hardware, and product teams.
Responsibilities
- Implement high-speed and power distribution network designs for ASIC packages
- Develop symbols, pad stacks, substrate routing, component placement, stack-ups, reference planes, and power distribution using package layout tools
- Optimize package pinouts and pin assignments based on system-level trade-offs
- Create methodologies that improve layout productivity, reliability, and delivery schedules
- Collaborate with package leads, signal integrity, power integrity, hardware, and product teams
- Plan and lead projects from initiation through completion while managing stakeholders
Requirements
- B.Sc. in Electrical Engineering, an Electrical Practical Engineer certificate, or equivalent experience
- At least 5 years of hands-on package or PCB layout experience
- Experience with high-speed design and signal integrity practices
- Significant experience with Cadence Virtuoso and APD (Allegro), SiP, or comparable PCB layout tools
- Knowledge of substrate or board manufacturing processes
Nice to have
- Experience with wire-bond and flip-chip package substrate layout
- Knowledge of Ansys SIwave or HFSS, or Cadence Sigrity or PowerSI
- Familiarity with Cadence SKILL and Python, Perl, or shell scripting