Senior CAD Engineer
Seeking an experienced CAD Engineer to modernize EDA infrastructure, develop CAD tools, and support IC design and verification for advanced semiconductor projects.
Responsibilities
- Modernize and upgrade design environment, EDA infrastructure, and in-house CAD tools.
- Support advanced technology nodes and improve engineering efficiency.
- Support design and verification activities of current and future semiconductor projects.
- Own and debug Physical Layout Verification checks including LVS, DRC, ERC, Antenna, and PERC signoff on complex SoC and mixed-signal designs.
Requirements
- B.Sc. / M.Sc. in Computer Science, Electrical Engineering, or a related field.
- Strong programming and scripting skills in C/C++, TCL, Python, and Linux shell scripting.
- Experience leveraging Generative AI tools for software development and automation.
- Solid understanding of IC design and verification flows.
- At least 5 years of hands-on experience with semiconductor EDA tools from Synopsys, Cadence, or Siemens EDA.
- Expertise in Physical Layout Verification, including LVS, DRC, ERC, Antenna, and PERC signoff checks.
Nice to have
- Experience with Siemens Calibre verification flows.
- RC extraction using StarRC and/or Calibre xACT.
- Experience with Git-based development flows.
- Experience in IC design and/or verification.