Physical Design STA Engineer
Join a technology-focused company to develop physical design, STA, and power integrity flows for cutting-edge networking silicon. Collaborate with block owners and full-chip STA engineers to ensure high-quality timing convergence. Requires B.Sc./M.Sc. in Electrical/Computer Engineering and 2+ years of relevant experience.
Responsibilities
- Develop physical design, STA, logic equivalence, and power integrity flows and methodologies for networking chips and SOCs.
- Work closely with block owners and full-chip STA engineers to assure high-quality and timely convergence.
- Create unique and creative solutions to state-of-the-art physical design problems.
- Participate and develop flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM, and back-end verification across multiple projects.
Requirements
- B.Sc./M.Sc. in Electrical Engineering/Computer Engineering or equivalent experience.
- 2+ years of fulltime relevant experience in physical design, STA, and timing closure methodologies.
- Proven experience and strong knowledge in physical design and STA with timing closure methodologies.
- Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation).
- Self-motivation, attention to detail, and good written, verbal, and presentation skills.
- Strong sense of ownership, self-learning skills, and ability to work independently and collaboratively.
Nice to have
- Experience in signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality), Backend CAD.
- Knowledge in Tcl/Perl/Python.
- Versatile and great teammate.