A
Junior Logic Design Engineer
·Israel
On-siteFull-timeHardware EngineeringSemiconductor Manufacturing
Join a team developing cutting-edge mixed-signal and high-speed IPs for FPGA and CPLD solutions. This entry-level role focuses on RTL design, simulation, and verification, collaborating with senior engineers to meet power, performance, and timing goals.
Responsibilities
- Assist in creating logic design, RTL code, and simulations for IP blocks and subsystems.
- Contribute to architectural and microarchitecture discussions under guidance.
- Learn and apply mixed-signal design concepts to support RTL development.
- Support optimization for power, performance, area, and timing.
- Participate in RTL verification, debug failing tests, and review results.
- Collaborate with internal teams and SoC customers for IP integration.
Requirements
- 0–2 years of experience in logic or digital design (internships count).
- Good understanding of digital design fundamentals, RTL (Verilog/SystemVerilog), and simulation.
- Strong problem-solving skills and eagerness to learn.
- B.Sc. (or upcoming graduate) in Electrical Engineering or related.
- Include academic grades sheet with application.
Nice to have
- Familiarity with communication interfaces or high-speed design.
- Exposure to mixed-signal concepts, SerDes, PHYs, or signal processing.