Junior ASIC Integration Engineer
Develop and integrate complex networking chips, collaborating with ASIC, physical design, CAD, package design, software, DFT, and verification teams.
Responsibilities
- Implement chip-level designs with cross-functional engineering teams
- Debug functional and structural design issues
- Support physical design readiness and emulation activities
- Perform chip-level partitioning, CDC, RDC, trial synthesis, and design quality checks
- Develop and deploy design flows and automation solutions
Requirements
- Bachelor’s or master’s degree in electrical engineering or computer engineering
- At least 2 years of chip design experience
- Hands-on RTL design experience with SystemVerilog
- Proficiency in at least one scripting language, such as Python, Bash, or Tcl
- Ability to collaborate effectively in cross-functional engineering teams
Nice to have
- Experience delivering designs to physical design, emulation, firmware, or other downstream customers
- Passion for design quality