DFT Design Engineer
Develop and integrate DFT features into complex SoCs, including SCAN, MBIST, and BSCAN. Drive test coverage, timing closure, and high-volume manufacturing test content. Collaborate with cross-functional teams to ensure high-quality semiconductor products.
Responsibilities
- Develop RTL design and simulation for DFT features such as SCAN, MBIST, and BSCAN.
- Provide DFT timing closure support and deliver test content to manufacturing.
- Define architecture and microarchitecture for blocks, subsystems, and SoCs under DFT design.
- Write and generate RTL and structural code for DFT integration.
- Optimize designs for power, performance, area, timing, test coverage, and test time reduction.
- Drive verification plans and debug failing RTL tests.
- Integrate DFT blocks into functional IP and SoC, and support SoC customers.
- Collaborate with post-silicon and manufacturing teams for silicon verification and debug.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 4+ years of DFT engineering experience.
- Strong knowledge of SCAN ATPG.
- Hands-on experience with RTL design, System Verilog, and digital design.
- Proficiency in EDA tools and techniques.
Nice to have
- Demonstrated problem-solving skills for complex design challenges.
- Strong communication and collaboration skills.
- Experience in driving innovative solutions for test coverage and efficiency.
- Commitment to continuous learning in DFT advancements.