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ASIC/RTL Logic Design Engineer – Camera
·Israel
Not specifiedFull-timeHardware EngineeringSemiconductors
We are seeking an experienced ASIC Front-End/RTL Logic Design Engineer to join a VLSI team focused on advanced camera and image processing technology. This role requires micro-architecture definition, RTL development, and collaboration across architecture, verification, and physical design teams.
Responsibilities
- Define micro-architecture from specifications.
- Develop and debug synthesizable RTL.
- Own digital design blocks from definition through implementation.
- Collaborate with Architecture, Verification, Physical Design, SW, and FW teams.
- Utilize digital design flows: simulation, synthesis, lint, and timing analysis.
Requirements
- 2–5 years of professional experience in Logic / RTL Design.
- Hands-on ASIC Front-End experience.
- Strong micro-architecture definition and RTL development/debug skills.
- Proficiency in Verilog / SystemVerilog.
- B.Sc. in Electrical Engineering, Computer Engineering, or related field.
Nice to have
- Experience in Image Processing / ISP.
- Knowledge of pixel processing, filters, or convolution.
- Scalable hardware design experience.
- Familiarity with synthesis, lint, timing analysis, and formal verification.
- Understanding of HW interaction with SW/FW.