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Senior Verification Engineer, Mixed-Signal DSP and PHY
לא צויןמשרה מלאהQA & Test AutomationCloud ComputingEnterprise SoftwareSemiconductor Manufacturing
Lead system-level verification for high-speed physical-layer silicon, validating digital DSP interaction with analog front ends across mixed-signal boundaries.
תחומי אחריות
- Lead verification strategy and define top-level integration test plans for 112G and 224G high-speed PHYs.
- Architect and implement mixed-signal verification flows using Real Number Modeling or SystemVerilog-AMS.
- Build testbenches for adaptive-algorithm stability, convergence, and tracking across process, voltage, and temperature corners.
- Develop tests for link bring-up, auto-negotiation, and error-recovery protocols under realistic data-center conditions.
- Coordinate with Signal Integrity, Power Integrity, and Analog teams to model channel impairments in the design-verification environment.
- Validate system-level interactions between analog front ends and digital DSP.
דרישות
- Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- At least 8 years of design-verification experience focused on mixed-signal systems, PHY layers, DSP, communication systems, or arithmetic logic blocks.
- Experience using Python, Perl, or Makefiles for verification automation.
יתרון
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with verilog-AMS, Real Number Modeling, or SystemVerilog-AMS.
- Experience leading verification from planning through tape-out across a full silicon lifecycle.
- Experience with throughput, latency, and power modeling.
- Experience with formal verification tools such as JasperGold for complex state machines.
- Understanding of adaptive algorithms such as FFE, DFE, LMS, and Zero-Forcing, including loop-stability verification.