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Senior Physical Design Engineer

Astera Labs·ישראל·en
לא צויןמשרה מלאהHardware EngineeringSemiconductors

Join a growing Israeli R&D team to own physical implementation and signoff for advanced connectivity chips, while helping establish backend methodologies and engineering standards.

תחומי אחריות

  • Own physical implementation from synthesis through floorplanning, place and route, and clock-tree synthesis
  • Lead macro-level implementation, floorplanning, and complex routing
  • Own timing signoff, physical verification, and reliability analysis
  • Apply logic equivalence checking and other verification techniques to ensure design correctness
  • Help define and improve backend methodologies, workflows, and tool automation
  • Collaborate with architecture, design, and DFT teams on advanced process nodes and high-speed connectivity
  • Help establish backend execution practices and technical standards for the local team

דרישות

  • Bachelor’s degree in Electrical Engineering or a related technical field
  • At least 3 years of hands-on physical design experience at a semiconductor company
  • Experience with the full RTL-to-GDS flow, including macro-level implementation, floorplanning, and complex routing
  • Experience with advanced process technologies at 7 nm or below
  • Experience with STA, logic equivalence checking, DRC, and EMIR signoff analysis
  • Proficiency in TCL or Python scripting for EDA flows and task automation

יתרון

  • Full-chip implementation and integration experience
  • Power and noise analysis knowledge, including SI/PI
  • Familiarity with DFT requirements and their impact on physical layout
  • Experience with Synopsys Fusion Compiler or ICC2, or Cadence Innovus
  • Background in high-speed interface designs or connectivity protocols

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