Senior Physical Design Engineer
Join a networking silicon engineering team designing high-speed communication chips. Work on challenging block and top-level designs, optimizing power, performance, and area.
תחומי אחריות
- Perform block- and top-level physical design to meet specifications and power, performance, and area constraints.
- Resolve complex timing and congestion issues across high-cell-count and high-speed designs.
- Work across RTL-to-GDS implementation, including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
- Contribute to physical design flow development.
- Serve as the technical lead and focal point for partition- or unit-level physical design.
דרישות
- Bachelor’s or master’s degree in electrical or computer engineering.
- At least 5 years of physical design experience.
- Experience with RTL-to-GDS flows and methodologies.
- Knowledge of physical design flows, including place and route, static timing analysis, and physical verification.
- Familiarity with EDA tools such as Synopsys or Cadence.