Senior Physical Design Engineer
Join a high-performance silicon engineering team developing advanced networking chips. Own block and top-level physical design across RTL2GDS flows while solving complex power, timing, area, and congestion challenges.
תחומי אחריות
- Perform block and top-level physical design according to power, area, and performance constraints
- Resolve complex timing and congestion issues
- Execute synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification
- Contribute to physical design flow development
- Serve as the technical leader and focal point for partition- or unit-level physical design
דרישות
- Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering
- At least 5 years of physical design experience
- Proven experience with RTL2GDS flows and methodologies
- Knowledge of PNR, static timing analysis, and physical verification flows
- Ability to collaborate effectively in a team
יתרון
- Familiarity with Synopsys, Cadence, or similar physical design EDA tools
- Experience with high-cell-count or high-speed design blocks