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Senior Physical Design Engineer
במקום העבודהמשרה מלאהHardware EngineeringSemiconductor ManufacturingElectronics Manufacturing
A technology company is seeking a senior engineer to develop full-chip physical design methodologies and physical verification flows for high-speed networking chips and system-on-chip products.
תחומי אחריות
- Develop full-chip physical design methodologies.
- Develop and support physical verification flows across multiple projects.
- Run, debug, and approve physical verification flows.
- Support tapeout activities for networking chips and system-on-chip designs.
- Collaborate with full-chip layout owners, block owners, and project managers to achieve high-quality, timely convergence.
- Create solutions for complex full-chip physical design and verification challenges.
- Develop flow and tool methodologies for full-chip physical design verification.
דרישות
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or equivalent experience.
- At least 5 years of hands-on full-chip layout and physical verification experience.
- Strong knowledge of physical verification methodologies, including DRC, LVS, antenna, ERC, and DFM in advanced process nodes.
- Proficiency with Python, Tcl, shell scripting, and Make.
- Experience working in Linux environments.
- Familiarity with physical design tools such as Synopsys ICC2 or Fusion Compiler and Cadence Innovus.
- Familiarity with physical verification tools such as Synopsys ICV and Siemens Calibre.
- Strong attention to detail, self-motivation, and interpersonal skills.
יתרון
- Experience with data collection and analysis.
- Experience defining methodologies or owning full-chip and place-and-route flows.
- Orientation toward AI tools or willingness to learn.
- Ability to work autonomously and collaborate effectively.