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RTL Design Engineer, SOC Clocking
לא צויןמשרה מלאהHardware EngineeringSemiconductors
Own SOC clocking and reset logic for next-generation networking chips, taking synthesizable RTL from micro-architecture specification through physical implementation and tape-out in collaboration with cross-functional engineering teams.
תחומי אחריות
- Own synthesizable RTL for SOC clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization through tape-out.
- Define the SOC clock and reset architecture with the micro-architecture team, gathering unit requirements and creating a coherent, verifiable design.
- Own clock-domain crossing infrastructure and closure across the SOC.
- Review specifications and provide feedback on implementation cost, timing, area, and power.
- Collaborate with physical design on clock-tree implementation and constraints, partitioning, floorplanning, synthesis, congestion, timing convergence, and design readiness.
- Support software and firmware teams with clock programming sequences, DVFS, and low-power and clock-shutdown flows.
- Drive design quality through lint, CDC/RDC, formal, synthesis QoR, connectivity, and structural checks.
- Support SOC chip build and assembly, and develop automation for repeatable RTL integration and design-quality checks.
- Support emulation, firmware, and post-silicon bring-up teams using the design.
דרישות
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
- At least 3 years of relevant RTL or logic design experience.
- Hands-on experience with Verilog or SystemVerilog and understanding of synthesis, timing, and the physical effects of RTL choices.
- Experience taking a design from micro-architecture specification through verification and physical implementation.
- Understanding of clock gating, clock muxing and dividers, glitchless switching, reset synchronization, and clock-domain crossing.
- Familiarity with lint, CDC/RDC, formal checks, and synthesis tools.
יתרון
- Prior ownership of SOC-level clocking or reset architecture on a taped-out chip.
- Experience integrating PLLs or clock generators and developing clock-tree constraints with backend teams.
- A track record of delivering clean designs to physical design, verification, emulation, firmware, and other downstream teams.