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RTL Design Engineer
לא צויןמשרה מלאהHardware EngineeringCloud ComputingInternet Services
Develop custom ASIC and SoC intellectual property from proof of concept through production, including IP microarchitecture, RTL coding, quality checks, and design-flow improvements.
תחומי אחריות
- Define IP-level microarchitecture, including interface protocols, block diagrams, transaction flows, and pipelines.
- Develop and debug RTL in Verilog or SystemVerilog.
- Debug functional and performance simulations and run Lint, CDC, formal verification, and UPF checks.
- Contribute to synthesis, timing and power closure, and ASIC silicon bring-up.
- Contribute to verification test plans and block- and SoC-level coverage analysis.
- Help improve design flows and methodologies, including design-generation automation.
דרישות
- Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
- At least 4 years of experience with digital logic design, RTL concepts, and Verilog or SystemVerilog.
- Experience in logic design and debug with design verification.
- Experience with microarchitecture and specifications.
יתרון
- Experience optimizing RTL synthesis, performance, power, and low-power design.
- Familiarity with design sign-off tools such as Lint, CDC, or VCLP.
- Scripting experience with Python or Perl.
- Knowledge of SoC architecture, assertion-based formal verification, or PCIe, UCIe, DDR, AXI, or ARM processors.
- Knowledge of high-performance and low-power design techniques.