Junior Physical Design Engineer
Develop physical designs for high-speed networking silicon, optimizing power, area, and performance across RTL-to-GDS flows.
תחומי אחריות
- Perform block-level physical design according to specifications and power, area, and performance constraints.
- Resolve complex timing and congestion issues in high-cell-count and high-speed blocks.
- Execute RTL-to-GDS development activities, including synthesis, power and clock distribution, place and route, timing closure, power analysis, noise analysis, and physical verification.
- Contribute to physical design flow development.
דרישות
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or equivalent experience.
- At least 2 years of relevant experience.
- Experience with RTL-to-GDS flows and methodologies.
- Knowledge of physical design flows, including place and route, static timing analysis, and physical verification.
- Understanding of physical construction and integration.
- Knowledge of LVS and DRC verification methodologies.
- Familiarity with physical design EDA tools such as Synopsys and Cadence.
- Collaborative teamwork skills.