Junior Physical Design Engineer
Join a networking silicon team to optimize power across physical design and contribute to chip development from RTL to GDS.
תחומי אחריות
- Optimize power for physical-design blocks and top-level designs under challenging constraints.
- Improve power across chip development stages, including synthesis, power and clock distribution, place and route, timing closure, and power and noise fixes.
- Perform power estimation and power modeling.
דרישות
- At least 1 year of experience in physical design and/or back-end power optimization.
- Familiarity with physical design EDA tools such as Synopsys or Cadence.
- Ability to use modern AI tools to improve engineering workflows, productivity, and problem-solving.
- A bachelor's or master's degree in electrical or computer engineering, or equivalent experience.
יתרון
- Knowledge of physical design flows and methodologies, including place and route, static timing analysis, and physical verification.
- Front-end design experience.