Junior Physical Design CAD Engineer
Develop physical design, static timing analysis, logic equivalence, power integrity, and backend verification flows for networking chips and SoCs.
תחומי אחריות
- Develop physical design, static timing analysis, logic equivalence, power integrity, and implementation flows for networking chips and SoCs
- Collaborate with block owners and full-chip timing engineers to achieve high-quality, timely convergence
- Develop flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, electromigration, and backend verification
- Create solutions for complex physical design challenges across multiple projects
דרישות
- Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering, or equivalent experience
- At least 2 years of relevant full-time experience
- Strong knowledge of physical design, backend CAD, static timing analysis, and timing closure methodologies
- Experience with industry-standard tools such as PrimeTime and PrimePower
- Strong written, verbal, and presentation skills
- Ability to work independently and collaboratively with internal and global teams
יתרון
- Experience with signoff tools and domains such as PrimeTime, PrimePower, RedHawk, or Formality
- Knowledge of Tcl, Perl, or Python