ASIC Physical Design CAD Engineer
Full-time role in Caesarea, Israel, supporting backend methodology and CAD flow development for advanced networking ASICs. The role covers RTL-to-GDS design flows and physical design optimization.
תחומי אחריות
- Develop and optimize CAD methodologies and tools for RTL-to-GDS flows
- Support chip definition, physical synthesis, place and route, and optimization
- Drive timing closure and design floorplanning
- Contribute to physical design integration and verification
- Improve the quality and efficiency of backend chip design flows
- Support adoption of new technologies and integration of design tools
דרישות
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering
- At least 2 years of relevant hands-on experience
- Experience in backend VLSI design
- Strong understanding of place-and-route flows
יתרון
- Deep knowledge of physical construction and integration
- Experience with LVS, DRC, and formal verification
- Experience with physical design CAD and EDA tools such as Synopsys and Cadence
- Ability to support technology adoption and new tool integration
- Ability to work independently and learn quickly