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Develop and optimize GPU-based inference infrastructure for large language models, improving performance, efficiency, and scalability.

Verify design-for-test (DFT) designs and implementations for chip projects. Define verification scope, build verification infrastructure, and execute test and coverage plans.

Join a networking software architecture team developing programmable RDMA transport protocols for large-scale AI systems. Shape architecture and roadmaps, explore hardware and software solutions, and evaluate innovations through prototypes, experiments, and quantitative modeling.

Design architecture and roadmaps for programmable RDMA transport protocols in an AI networking stack. Evaluate new hardware and software approaches for next-generation platforms.

Design and advance programmable RDMA networking architecture for next-generation AI systems. Translate requirements into architecture and roadmaps, and evaluate innovations through prototypes, experiments, and quantitative modeling.

Design and deliver security architecture for next-generation confidential computing network devices, with a focus on hardware isolation and secure platforms.

Design and implement security architectures for next-generation confidential computing devices, with a focus on attestation systems, hardware isolation, and secure platforms.

Design and deliver next-generation confidential computing architectures for network devices and secure platforms.

Develop physical designs for networking silicon, optimizing power, performance, and area across the RTL-to-GDS flow.

Build software tools for chip design and verification workflows, working with designers and verification engineers to improve productivity and quality.